It is known in the art to operate an integrated memory circuit (such as an SRAM) at a plurality of supply voltages. For example, an integrated memory circuit may be supplied with a relatively high supply voltage (for example, 1.26V) in one mode of operation and further supplied with a relatively low supply voltage (for example, 0.6V) in another mode of operation.
In a typical integrated memory circuit, a sense amplifier coupled to the bit line(s) of a memory column is enabled for operation in response to a sense amplifier enable (SAEN) signal. The SAEN signal is generated by a sense amplifier enable generator circuit that implements a delay of sufficient time after selection of the memory cell (bitcell) to permit the data signals on the bit lines to fully develop before the sense amplifier is activated to sense those data signals. The amount of time needed to ensure that the data signals on the bit lines have fully developed varies as a function of the supply voltage for the integrated memory circuit. For example, the required amount of time is relatively longer for relatively lower supply voltages as the worst memory cell (bitcell) degrades heavily with low voltage and tracking it needs a long amount of time at low supply voltage.
Reference is now made to FIG. 1 showing a block diagram for a prior art self-timing solution for a sense amplifier enable generator circuit 10 used within an integrated memory circuit 12. The circuit 12 includes a memory array 14 formed by a plurality of rows and columns. The columns include a plurality of columns in an active portion 16 of the array 14 as well as at least one column in a dummy portion 18 of the array. In the active portion 16, each column is defined by a pair of bit lines that are complementary and noted as bit line BL and bit line bar BLB, with a memory cell 20 coupled between the pair of bit lines BL, BLB at each row location and driven a corresponding word line WL. In the dummy portion 18, each column is defined by at least one bit line noted as dummy bit line DBL, with a dummy memory cell 22 coupled to the dummy bit line DBL at each row location and driven by a dummy word line DWL.
Although multiple cells 20 and 22 are shown for single column, the illustration of FIG. 1 is simplified to explicitly show only the word line WL for one row with the corresponding memory cell 20 (in one column) for that row and only the dummy word line DWL for one row with the corresponding dummy memory cell 22 (in another column) for that row. The word lines WL and DWL are driven by a row decoder circuit 26 which operates to decode an address ADD and select, based on the decoded address, one word line WL for actuation. The dummy word line DWL is simultaneously activated with the activation of any address selected word line WL.
A sense amplifier circuit 30 is coupled to the plurality of pairs of bit lines through a column multiplexing circuit 32. The sense amplifier circuit 30 includes a plurality of sense amplifiers 36, with only one shown in the simplified illustration of FIG. 1. The sense amplifiers 36 are actuated for operation in response a sense amplifier enable (SAEN) signal generated by the sense amplifier enable generator circuit 10. The sense amplifier enable generator circuit 10 is coupled to the dummy bit line DBL and functions to sense the voltage on the dummy bit line DBL. In response to row decoder assertion of the signal on the dummy word line DWL (reference 50, FIG. 2), the dummy memory cell 22 is configured to discharge the dummy bit line DBL. As a result, the voltage on the dummy bit line DBL falls (reference 52, FIG. 2). The sense amplifier enable generator circuit 10 compares the falling voltage on the dummy bit line DBL to a threshold voltage, and when that threshold voltage is crossed the sense amplifier enable generator circuit 10 asserts the SAEN signal (reference 54, FIG. 2) and actuates the plurality of sense amplifiers 36 in the sense amplifier circuit 30. The threshold voltage is selected to ensure a sufficient time delay between assertion of the word line signals WL and DWL and crossing of the threshold so that such actuation of the sense amplifier circuit does not occur until such time as the data signals on the bit lines BL, BLB coupled to memory cell 20 have fully developed.
The column multiplexing circuit 32 is controlled to selectively connect bit line pairs to the sense amplifiers 36 of the sense amplifier circuit 30 by a column decoder circuit 40 in response to the decoded address ADD. The configuration and operation of column multiplexed memory circuits is well known to those skilled in the art.
Reference is now made to FIG. 3 showing additional circuit details for the sense amplifier enable generator circuit 10. The sense amplifier enable generator circuit 10 functions also to precharge the dummy bit line DBL. A control circuit 60 applies a precharge signal PRE to the gate of a MOS transistor 62 having a source terminal coupled to a supply node (vdd) and a drain terminal coupled to the dummy bit line DBL. In response to assertion logic low of the precharge signal PRE (reference 56, FIG. 2), the MOS transistor 62 turns on and pulls the dummy bit line DBL up to the supply node (vdd) voltage. This precharge operation occurs prior to a read of the memory. When the precharge signal PRE is deasserted (reference 58, FIG. 2), the voltage on the dummy bit line DBL may then be discharged in response to the assertion of the signal on the dummy word line DWL (reference 50, FIG. 2).
A comparator circuit 64 has a first input connected to the dummy bit line DBL and a second input connected to receive the threshold voltage. The comparator circuit 64 functions to compare the voltage on the dummy bit line DBL to the threshold voltage. The voltage on the dummy bit line DBL falls (reference 52, FIG. 2) in response to assertion of the dummy word line DWL signal. When the voltage on the dummy bit line DBL falls below the threshold voltage, the output of the comparator circuit 64 changes logic state and the SAEN signal is asserted (reference 54, FIG. 2).
As discussed above, the memory circuit may operate at a plurality of supply voltages. The operation shown in FIG. 2 and described above is representative of the operation of the memory circuit when supplied with a relatively high supply voltage (for example, 1.26V). When supplied with a relatively low supply voltage (for example, 0.6V), the precharge voltage on the dummy bit line DBL will be correspondingly lower, but the threshold voltage will remain the same. As noted above, there is a large degradation of the worst bitcell (for example, six sigma away from nominal due to local statistical variation) at the lower supply voltage. Because of this, the delay generated by the sense amplifier enable generator circuit 10 is not tracked from higher to lower supply voltage. The discharge time for the dummy bit line DBL will degrade with reduction of the supply voltage. However, the dummy memory cell 22 only tracks the nominal case rather than the worst case. As a result, when operating at the lower supply voltage, the output of the comparator circuit 64 may change logic state too soon and the SAEN signal may be asserted too early. If this occurs, there is a risk that the sense amplifier 36 will be enabled prior to the time when the data signals on the bit lines BL, BLB have fully developed. An incorrect read of the data for data output from the sense amplifier 36 may then occur.
The prior art teaches a number of solutions to the foregoing problem. In one solution, the memory circuit slows the discharge rate of the dummy bit line DBL using an added charged capacitance when operating at the relatively low supply voltage. A switching circuit, such as a pass gate, is typically used to selectively connect the added capacitance when operating in low supply voltage mode, but this pass gate is somewhat resistive and this circuitry adversely affects operation to fully discharge the dummy bit line. In another solution, the memory circuit logically delays the SAEN signal using a multiplexer circuit when operating at the relatively low supply voltage. However, there is no correlation between the degradation over time of the logic delay and the degradation over time of the memory cells. So, as the memory circuit ages, proper timing of the assertion of the SAEN signal relative to the full development of the data signals on the bit lines BL, BLB cannot be assured.
There is a need in the art to provide a better solution.